In the Internet of things (IoT), network devices and mobile systems should exchange a considerable amount of data with negligible\ndelays. For this purpose, the community has used the software-defined networking (SDN), which has provided high-speed flowbased\ncommunication mechanisms. To satisfy the requirements of SDN in the classification of communicated packets, highthroughput\npacket classification systems are needed. A hardware-based method of Internet packet classification that could be\nsimultaneously high-speed and memory-aware has been proved to be able to fill the gap between the network speed and the\nprocessing speed of the systems on the network in traffics higher than 100 Gbps. The current architectures, however, have not been\nsuccessful in achieving these two goals. This paper proposes the architecture of a processing micro-core for packet classification in\nhigh-speed, flow-based network systems. By using the hashing technique, this classifying micro-core fixes the length of the rules\nfield. As a result, with a combination of SRAM and BRAM memory cells and implementation of two ports on Virtex................
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